The present invention relates to testing integrated circuits and, more particularly, to a low power scan flip-flop cell.
Scan chains comprise a plurality of interconnected scan flip-flops and are used to obtain access to internal nodes of an integrated circuit (IC) to simplify testing of the IC by passing test data through the flip-flops. The scan flip-flop is configured to operate in one of two modes, functional mode and scan mode.
When the scan enable input of a scan flip-flop is set to logic low, the scan flip-flop is in the functional mode; when the scan enable input of the scan flip-flop is set to logic high, the scan flip-flop is in scan mode (in this example, the scan enable signal is high active). For a full scan design, during scan testing, all of the flip-flops and all of the combinational logic connected to the flip-flops, may be toggling at the same time, causing very high power consumption. This high power consumption is much greater than the power consumption in normal functional mode where only some of the combinational logic and flip-flops are toggling, and such high power consumption may exceed the circuit's power rating. Further, as IC chip density and speed increase, the scan shift power problem is exacerbated.
Therefore, there is a need for providing a low power scan flip-flop cell and scan chain to solve the above problems.